1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including highly scaled transistor elements having a double gate (FinFET) or triple gate architecture.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, silicon dioxide is preferably used as a gate insulation layer in field effect transistors that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET).
It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Although significant advantages may be obtained with respect to performance and controllability of sophisticated planar transistor architectures on the basis of the above-specified strategies, in view of further device scaling, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width while at the same time maintaining good controllability of the current flow through the channel region. To this end, so-called FinFETS have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein, on both sidewalls, a gate dielectric material and a gate electrode material may be provided, thereby realizing a double gate transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the silicon fin is on the order of 10 nm and the height thereof is on the order of 30 nm. In a modified version of the basic double gate transistor architecture, a gate dielectric material and a gate electrode may also be formed on a top surface of the fin, thereby realizing a tri-gate transistor architecture. With reference to FIGS. 1a-1b, the basic configuration of conventional FinFETS and characteristics associated with the conventional manufacturing techniques may be described in more detail.
FIG. 1a schematically illustrates a perspective view of a semiconductor device 100 which comprises a conventional double gate or fin field effect transistor (FinFET) 150. As illustrated, the device 100 may comprise a substrate 101, such as a silicon substrate, having formed thereon a buried insulating layer 102, for instance in the form of a silicon dioxide material. Moreover, in FIG. 1a, a fin 110 is illustrated which represents the remaining portion of a silicon layer (not shown) formed on the buried oxide layer 102, thereby defining an SOI configuration. The fin 110 may comprise a portion of drain and source regions 111 and also a channel region (not shown), which may be covered by gate electrode structures 120A, 120B which may be formed on respective sidewalls 110A, 110B of the fin 110 and may comprise an appropriate gate dielectric material, such as silicon dioxide in combination with an electrode material, such as polycrystalline silicon. A top surface of the fin 110 may be covered by a cap layer 112, which may be comprised of silicon nitride and the like. As illustrated, both gate electrode structures 120A, 120B may be connected by electrode material formed on the cap layer 112. The fin 110 may have a height 111H, a width 111W and a length 111L corresponding to the overall device requirements, wherein an effective channel length within the fin 110 may be substantially determined by an extension of the gate electrode structures 120A, 120B along the length direction defined by the fin 110.
Typically, the semiconductor device 100 comprising the FinFET 150 is formed by patterning the active silicon layer formed on the buried insulating layer 102 and thereafter performing appropriately designed manufacturing processes for forming the gate electrode structures 120A, 120B, defining appropriate dopant profiles for the drain and source regions 111 and the channel region, followed by forming an appropriate contact layer.
During operation, a current flow may be established from drain to source by applying an appropriate supply voltage and also applying an appropriate control voltage to the gate electrodes 120A, 120B. Consequently, the channel region, i.e., the portion of the fin 110 enclosed by the gate electrode structures 120A, 120B, may be controlled from both sides of the fin 110, thereby obtaining a fully depleted configuration, which is expected to provide enhanced channel control.
FIG. 1b schematically illustrates a top view of the device 100, in which three FET transistors 150 are provided. As illustrated, the drain regions of the transistors 150 and the source regions may be connected by an epitaxially re-grown silicon material, thereby forming a silicon layer 103 at the drain side and the source side, respectively. Typically, the silicon material at the drain side and the source side may be formed by selective epitaxial growth techniques, thereby also requiring spacer elements 104 to provide the required offset to the gate electrode material of the various double gate structures 120A, 120B. Although the semiconductor layers 103 may be provided at the drain side and the source side, acting as drain and source regions of the individual transistor cells 150, nevertheless, a portion of the drain and source regions, such as the regions 111 (see FIG. 1a), may have to be provided due to the presence of the spacer elements 104, thereby creating a moderately high series resistance due to the limited amount of silicon volume in the fins and due to dopant out-diffusion into the buried oxide. Consequently, although these transistors offer superior short channel behavior due to the full depletion of the channel and due to control from two or three gates, when the cap layer 112 (see FIG. 1a) is omitted and replaced by a gate dielectric material, drive current is limited by the high series resistance of the drain and source regions 111 in the fins 110 within each individual transistor 150, so that currently this technology may not be competitive to standard planar transistor architecture that may be provided in a bulk configuration or partially depleted SOI configuration.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.